RISC-V /Debug /Debug Control and Status (dcsr)

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Interpret as Debug Control and Status (dcsr)

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0prv0 (step)step 0 (nmip)nmip 0 (disabled)mprven 0 (v)v0cause0 (normal)stoptime 0 (normal)stopcount 0 (interrupts disabled)stepie 0 (exception)ebreaku 0 (exception)ebreaks 0 (exception)ebreakm 0 (exception)ebreakvu 0 (exception)ebreakvs 0 (NO_LP_EXPECTED)pelp 0 (disabled)cetrig 0 (critical error)extcause 0 (none)debugver

cetrig=disabled, pelp=NO_LP_EXPECTED, ebreaku=exception, stopcount=normal, ebreakvs=exception, extcause=critical error, ebreakvu=exception, stepie=interrupts disabled, ebreaks=exception, stoptime=normal, ebreakm=exception, debugver=none, mprven=disabled

Description

Upon entry into Debug Mode, {dcsr-v} and {dcsr-prv} are updated with the privilege level the hart was previously in, and {dcsr-cause} is updated with the reason for Debug Mode entry. Other than these fields and {dcsr-nmip}, the other fields of {csr-dcsr} are only writable by the external debugger.

tab:dcsrcausepriority shows the priorities of reasons for entering Debug Mode. Implementations should implement priorities as shown in the table. For compatibility with old versions of this spec, resethaltreq and haltreq are allowed to be at different positions than shown as long as:

  1. resethaltreq is higher priority than haltreq
  2. the relative order of the other four causes is maintained

Priority of reasons for entering Debug Mode from highest to lowest.

{dcsr-cause} encoding Cause
5 resethaltreq
6 halt group
3 haltreq
2 trigger (See tab:priority for detailed priority)
1 ebreak
4 step
đź“Ś NOTE

Note that mcontrol/mcontrol6 triggers which fire after the instruction which hit the trigger are considered to be high priority causes on the subsequent instruction. Therefore, an execute trigger with timing=after on an ebreak instruction is lower priority than the ebreak itself because the trigger will fire after the ebreak instruction. For the same reason, if a single instruction is stepped with both icount and {dcsr-step} then the {dcsr-step} has priority. See tab:priority for the relative priorities of triggers with respect to the ebreak instruction.

Most multi-hart implementations will probably hardwire {dcsr-stoptime} to 0, as the implementation can get complicated and the benefit is small.

Fields

prv

Contains the privilege mode the hart was operating in when Debug Mode was entered. The encoding is described in tab:privmode. A debugger can change this value to change the hart’s privilege mode when exiting Debug Mode.

Not all privilege modes are supported on all harts. If the encoding written is not supported or the debugger is not allowed to change to it, the hart may change to any supported privilege mode.

step

When set and not in Debug Mode, the hart will only execute a single instruction and then enter Debug Mode. See stepbit for details.

The debugger must not change the value of this bit while the hart is running.

nmip

When set, there is a Non-Maskable-Interrupt (NMI) pending for the hart.

Since an NMI can indicate a hardware error condition, reliable debugging may no longer be possible once this bit becomes set. This is implementation-dependent.

mprven

0 (disabled): mprv in mstatus is ignored in Debug Mode.

1 (enabled): mprv in mstatus takes effect in Debug Mode.

v

Extends the prv field with the virtualization mode the hart was operating in when Debug Mode was entered. The encoding is described in tab:privmode. A debugger can change this value to change the hart’s virtualization mode when exiting Debug Mode. This bit is hardwired to 0 on harts that do not support virtualization mode.

cause

Explains why Debug Mode was entered.

When there are multiple reasons to enter Debug Mode in a single cycle, hardware should set {dcsr-cause} to the cause with the highest priority. See tab:dcsrcausepriority for priorities.

1 (ebreak): An ebreak instruction was executed.

2 (trigger): A Trigger Module trigger fired with action=1.

3 (haltreq): The debugger requested entry to Debug Mode using {dmcontrol-haltreq}.

4 (step): The hart single stepped because {dcsr-step} was set.

5 (resethaltreq): The hart halted directly out of reset due to {resethaltreq} It is also acceptable to report 3 when this happens.

6 (group): The hart halted because it’s part of a halt group. Harts may report 3 for this cause instead.

7 (other): The hart halted for a reason other than the ones mentioned above. {dcsr-extcause} may contain a more specific reason.

stoptime

0 (normal): time continues to reflect mtime.

1 (freeze): time is frozen at the time that Debug Mode was entered. When leaving Debug Mode, time will reflect the latest value of mtime again.

While all harts have {dcsr-stoptime}=1 and are in Debug Mode, mtime is allowed to stop incrementing.

stopcount

0 (normal): Increment counters as usual.

1 (freeze): Don’t increment any hart-local counters while in Debug Mode or on ebreak instructions that cause entry into Debug Mode. These counters include the instret CSR. On single-hart cores cycle should be stopped, but on multi-hart cores it must keep incrementing.

stepie

0 (interrupts disabled): Interrupts (including NMI) are disabled during single stepping with {dcsr-step} set. This value should be supported.

1 (interrupts enabled): Interrupts (including NMI) are enabled during single stepping with {dcsr-step} set.

ebreaku

0 (exception): ebreak instructions in U-mode behave as described in the Privileged Spec.

1 (debug mode): ebreak instructions in U-mode enter Debug Mode.

ebreaks

0 (exception): ebreak instructions in S-mode behave as described in the Privileged Spec.

1 (debug mode): ebreak instructions in S-mode enter Debug Mode.

ebreakm

0 (exception): ebreak instructions in M-mode behave as described in the Privileged Spec.

1 (debug mode): ebreak instructions in M-mode enter Debug Mode.

ebreakvu

0 (exception): ebreak instructions in VU-mode behave as described in the Privileged Spec.

1 (debug mode): ebreak instructions in VU-mode enter Debug Mode.

ebreakvs

0 (exception): ebreak instructions in VS-mode behave as described in the Privileged Spec.

1 (debug mode): ebreak instructions in VS-mode enter Debug Mode.

pelp

This bit is part of ((Zicfilp)) and only exists when that extension is implemented.

0 (NO_LP_EXPECTED): No landing pad instruction expected.

1 (LP_EXPECTED): A landing pad instruction is expected.

cetrig

This bit is part of ((Smdbltrp)) and only exists when that extension is implemented.

0 (disabled): A hart in a critical error state does not enter Debug Mode but instead asserts the critical-error signal to the platform.

1 (enabled): A hart in a critical error state enters Debug Mode instead of asserting the critical-error signal to the platform. Upon such entry into Debug Mode, the cause field is set to 7, and the extcause field is set to 0, indicating a critical error triggered the Debug Mode entry. This cause has the highest priority among all reasons for entering Debug Mode. Resuming from Debug Mode following an entry from the critical error state returns the hart to the critical error state.

extcause

When {dcsr-cause} is 7, this optional field contains the value of a more specific halt reason than “other.” Otherwise it contains 0.

0 (critical error): The hart entered a critical error state, as defined in the ((Smdbltrp)) extension.

debugver

0 (none): There is no debug support.

4 (1.0): Debug support exists as it is described in this document.

15 (custom): There is debug support, but it does not conform to any available version of this spec.

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